The present invention relates generally to the field of semiconductor memories; more particularly, to dynamic random-access memories (DRAMS) and memory architectures that provide for DRAM refresh operations.
Advances in central processor unit (CPU) performance and chipset density have outpaced improvements in memory bandwidth performance. One reason for this anomaly lies in the physical device characteristics and requirements of the components that make up the computer""s memory subsystem.
In a standard computer system, the main or system memory is typically implemented with DRAM devices. In a DRAM, data is stored in a memory cell in the form of a capacitive charge that decays over time. To preserve the integrity of the data, periodic refreshing of the cell must occur in order to restore the charge level to its original, full capacity. In a typical refresh operation, which usually is performed every few milliseconds, the data is read and then rewritten back into the memory. In many cases, explicit refresh cycles occur to specified memory address at the direction of the subsystem memory controller. Reading or writing data to an addressed location in memory is another way that memory cells can be refreshed. (In the context of this specification, an explicit refresh cycle is called a primary refresh cycle. Refreshes that result from a read or write operation to a memory location are referred to as secondary refreshes.)
The problem, of course, is that normal memory activity (i.e., read and write accesses) cannot occur during the time that refresh operations are taking place. Refresh cycles thereforexe2x80x94while necessary for dynamic RAM subsystem operationxe2x80x94consume otherwise useful memory bandwidth.
In current dynamic RAM subsystems, a single timer, or a small set of timers controls primary refresh operations. The timer is set to an appropriate interval so as to insure that a refresh operation occurs before a known time it takes a DRAM cell to become completely discharged. When the timer expires, a primary refresh cycle is posted for execution. Generally, a sequential timer or counter is used to generate the address for the primary refresh cycle. The primary refresh cycle, with its address, is sent on to logic that either executes the cycle or posts it for later execution. An example of this latter approach is found in U.S. Pat. No. 5,907,857, which teaches refreshing dynamic memory in a burst that shifts memory refresh activity into periods of time in which the memory bus is relatively idle.
Various approaches have been developed to avoid the degradation of performance caused by imposing fixed interval refresh cycles on a DRAM. By way of example, U.S. Pat. No. 5,822,265 teaches a DRAM controller that performs a background refresh during times when the memory request input of the DRAM is idle after a measured time interval substantially less than the maximum refresh interval. U.S. Pat. No. 5,828,382 describes a method of interleaving refresh cycles to improve DRAM speed by reducing the time needed for a precharge sequence during a refresh cycle. The method involves grouping two or more consecutive refresh cycles, thereby effectively reducing precharge time per refresh operation.
Another improvement in the field is taught in U.S. Pat. No. 5,774,404, which discloses a DRAM having a refresh function that adjusts the refresh period according to the temperature-dependent data hold time of memory cells to reduce standby current.
Despite past efforts to overcome the memory bandwidth problem, computer systems utilizing DRAMs still suffer from a refresh overhead that can be as high as 15%. Consequently, there is an unfulfilled need for a new approach to improve memory subsystem performance.